SOI-CMOS-MEMS Electrothermal Micromirror Arrays for Scanning Applications
Peter Gilgunn, Congzhong Guo, Gary Fedder
(a) SEM image of an SOI-CMOS-MEMS micromirror pixel. (b) Optical images of an actuated micromirror array. (c) Micromirror array configuration for laser range finding application.
Electrothermally actuated micromirrors set the benchmark for optical scan range in MEMS-based mirror devices, but have not provided the reflective area density, or fill factor, necessary for arrayed applications, such as spatial light modulators (SLMs).
This project is focused on the development of a fabrication technology that produces optical scan ranges of 180 degrees with fill factors of > 90%. The fabrication technology is called SOI-CMOS-MEMS as it hybridizes silicon-on-insulator (SOI) payloads with CMOS-MEMS actuators. The hybridization provides for independent optimization of an SOI mirror and a CMOS-MEMS electrothermal actuator (see images (a) and (b) above). The use of CMOS-MEMS enables the integration of onboard sensing, control, and signal conditioning functions. Fundamental research conducted as part of the process development led to modeling of aspect ratio dependent etching (ARDE) during deep reactive ion etch (DRIE) and heating of suspended structures during microstructure release etch.
The performance of SOI-CMOS-MEMS electrothermally actuated mirror devices allows us to move into areas of the application space that require high fill factor but have other criteria that make electrostatically actuated mirrors unsuitable. SOI-CMOS-MEMS mirrors are capable of operating at < 5 V, compared to electrostatically actuated mirrors that typically operate above 20 V, an advantage that makes our mirrors ideal for autonomous applications like laser communications and ranging on micro air vehicles (uAV).
Alternative actuator designs with H-shaped coupling springs will be investigated as a means to achieve large angle 2-D scanning for sub-millimeter-scale mirror. Larger electrothermal sensitivity actuators will be investigated in other CMOS fabrication technologies.
This work is supported by The Boeing Company.