January/February 2002
Volume Two - Issue One



Phonon Transport in Nanostructures with Applications to Ultra-Thin Silicon-On-Insulator (SOI) Transisters
Funding: NSF - Nanoscalse Interdisciplinary Research Team (NIRT), IBM and PITA

A Schematic of a Field
Effect Transistor (FET)
made on a SOI

Advances in microfabrication processes have led to a continuous miniaturization of microelectronic and data storage devices as well as MicroElectroMechanical Systems (MEMS) (e.g., mechanical and chemical sensors) that contain semiconductor or metallic layers only a few nanometers thick. The performance and reliability of microelectronic and data storage devices (systems) are influenced by transport of thermal energy in multilayer structures. Because the thermal phenomena are not directly responsible for the electrical or optical functionality of these devices, they often receive only indirect consideration during system design. The situation is however changing rapidly as dimensions of these devices approach several nanometers and timescales of their operation gets closer to the nano- to pico-seconds range. Silicon-on-insulator circuits promise advantages in speed and processing cost compared to circuits made from bulk silicon. Around the year 2000, IBM built and tested SOI-based microprocessors that have 20 to 25% faster circuit speed compared to CMOS technology made on bulk silicon substrates (See figure). The source of increased SOI performance is the elimination of area junction capacitance and the "body effect" in bulk CMOS technology. However, the buried silicon-dioxide layer in SOI circuits has a very low thermal conductivity (~1 W m-1 K-1) compared to the silicon device layer. This results in a relatively large thermal resistance between the device and the chip packaging. The thermal conduction or phonon transport in the silicon device layer strongly influences the peak temperature rise in SOI devices.

Recently, a multidisciplinary faculty, research associates and students from the Institute for Complex Engineered Systems (ICES), Mechanical, Electrical and Computer, and Chemical Engineering Departments have received a $1,300,000 funding from National Science Foundation (NSF), and funding from the Pennsylvania Infrastructure Technology Alliance (PITA) to investigate in collaboration with IBM the "Phonon Transport in Nanostructures with Application to Ultra-Thin Silicon-On-Insulator (SOI) Transistors." This project focuses on the study of two major nanoscale phenomena: (a) phonon transport in single crystal silicon layer of thickness in the range of 10-50 nm and (b) ballistic phonon transport near hotspots (~10 nm) in the active region of silicon-on-insulator (SOI) transistors. The experimental part of the study involves the very first measurements of thermal conductivity of nanometer size, single crystal silicon layer and ballistic phonon transport near a hotspot in a transistor. The computational effort will focus on numerical simulations of phonon Boltzmann transport equation (BTE) in the relaxation time approximation, accounting for phonon dispersion as well as frequency dependent phonon mean free paths in silicon.

Researchers for the project include: Mehdi Asheghi, faculty, ME; Cristina H. Amon, faculty ME & director ICES; Gary K. Fedder, faculty, ECE; Myung S. Jhon, faculty, ChE; Jayathi Murthy, faculty, Purdue; and Shi-Chune Yao, faculty, ME. Student researchers: Mohamad S. Sadeghipour, Carlos Gomes, Sreekant Narumanchi, Yizhang Yang, Bahareh Behkam, Sartaj Ghai, Keivan Yazdani, Shahab Shojaeizadeh, Sartaj Ghai, Wenjun Liu and Shu Zhang

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